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dsputil_ppc.c
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1 /*
2  * Copyright (c) 2002 Brian Foley
3  * Copyright (c) 2002 Dieter Shirley
4  * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
5  *
6  * This file is part of FFmpeg.
7  *
8  * FFmpeg is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU Lesser General Public
10  * License as published by the Free Software Foundation; either
11  * version 2.1 of the License, or (at your option) any later version.
12  *
13  * FFmpeg is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16  * Lesser General Public License for more details.
17  *
18  * You should have received a copy of the GNU Lesser General Public
19  * License along with FFmpeg; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21  */
22 
23 #include <string.h>
24 
25 #include "libavutil/attributes.h"
26 #include "libavutil/cpu.h"
27 #include "libavutil/mem.h"
28 #include "dsputil_altivec.h"
29 
30 /* ***** WARNING ***** WARNING ***** WARNING ***** */
31 /*
32 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a
33 cache line size not equal to 32 bytes.
34 Fortunately all processor used by Apple up to at least the 7450 (aka second
35 generation G4) use 32 bytes cache line.
36 This is due to the use of the 'dcbz' instruction. It simply clear to zero a
37 single cache line, so you need to know the cache line size to use it !
38 It's absurd, but it's fast...
39 
40 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line
41 size: 128 bytes. Oups.
42 The semantic of dcbz was changed, it always clear 32 bytes. so the function
43 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
44 which is defined to clear a cache line (as dcbz before). So we still can
45 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
46 
47 see <http://developer.apple.com/technotes/tn/tn2087.html>
48 and <http://developer.apple.com/technotes/tn/tn2086.html>
49 */
50 static void clear_blocks_dcbz32_ppc(int16_t *blocks)
51 {
52  register int misal = ((unsigned long)blocks & 0x00000010);
53  register int i = 0;
54  if (misal) {
55  ((unsigned long*)blocks)[0] = 0L;
56  ((unsigned long*)blocks)[1] = 0L;
57  ((unsigned long*)blocks)[2] = 0L;
58  ((unsigned long*)blocks)[3] = 0L;
59  i += 16;
60  }
61  for ( ; i < sizeof(int16_t)*6*64-31 ; i += 32) {
62  __asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
63  }
64  if (misal) {
65  ((unsigned long*)blocks)[188] = 0L;
66  ((unsigned long*)blocks)[189] = 0L;
67  ((unsigned long*)blocks)[190] = 0L;
68  ((unsigned long*)blocks)[191] = 0L;
69  i += 16;
70  }
71 }
72 
73 /* same as above, when dcbzl clear a whole 128B cache line
74  i.e. the PPC970 aka G5 */
75 #if HAVE_DCBZL
76 static void clear_blocks_dcbz128_ppc(int16_t *blocks)
77 {
78  register int misal = ((unsigned long)blocks & 0x0000007f);
79  register int i = 0;
80  if (misal) {
81  // we could probably also optimize this case,
82  // but there's not much point as the machines
83  // aren't available yet (2003-06-26)
84  memset(blocks, 0, sizeof(int16_t)*6*64);
85  }
86  else
87  for ( ; i < sizeof(int16_t)*6*64 ; i += 128) {
88  __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
89  }
90 }
91 #else
92 static void clear_blocks_dcbz128_ppc(int16_t *blocks)
93 {
94  memset(blocks, 0, sizeof(int16_t)*6*64);
95 }
96 #endif
97 
98 #if HAVE_DCBZL
99 /* check dcbz report how many bytes are set to 0 by dcbz */
100 /* update 24/06/2003 : replace dcbz by dcbzl to get
101  the intended effect (Apple "fixed" dcbz)
102  unfortunately this cannot be used unless the assembler
103  knows about dcbzl ... */
104 static long check_dcbzl_effect(void)
105 {
106  register char *fakedata = av_malloc(1024);
107  register char *fakedata_middle;
108  register long zero = 0;
109  register long i = 0;
110  long count = 0;
111 
112  if (!fakedata) {
113  return 0L;
114  }
115 
116  fakedata_middle = (fakedata + 512);
117 
118  memset(fakedata, 0xFF, 1024);
119 
120  /* below the constraint "b" seems to mean "Address base register"
121  in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
122  __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
123 
124  for (i = 0; i < 1024 ; i ++) {
125  if (fakedata[i] == (char)0)
126  count++;
127  }
128 
129  av_free(fakedata);
130 
131  return count;
132 }
133 #else
134 static long check_dcbzl_effect(void)
135 {
136  return 0;
137 }
138 #endif
139 
141 {
142  const int high_bit_depth = avctx->bits_per_raw_sample > 8;
143  int mm_flags = av_get_cpu_flags();
144 
145  // Common optimizations whether AltiVec is available or not
146  if (!high_bit_depth) {
147  switch (check_dcbzl_effect()) {
148  case 32:
150  break;
151  case 128:
153  break;
154  default:
155  break;
156  }
157  }
158 
159 #if HAVE_ALTIVEC
160  if (mm_flags & AV_CPU_FLAG_ALTIVEC) {
161  ff_dsputil_init_altivec(c, avctx);
162  ff_int_init_altivec(c, avctx);
163  c->gmc1 = ff_gmc1_altivec;
164 
165 #if CONFIG_ENCODERS
166  if (avctx->bits_per_raw_sample <= 8 &&
167  (avctx->dct_algo == FF_DCT_AUTO ||
168  avctx->dct_algo == FF_DCT_ALTIVEC)) {
169  c->fdct = ff_fdct_altivec;
170  }
171 #endif //CONFIG_ENCODERS
172 
173  if (avctx->lowres == 0 && avctx->bits_per_raw_sample <= 8) {
174  if ((avctx->idct_algo == FF_IDCT_AUTO) ||
175  (avctx->idct_algo == FF_IDCT_ALTIVEC)) {
179  }
180  }
181 
182  }
183 #endif /* HAVE_ALTIVEC */
184 }