FFmpeg
cpu.c
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1 /*
2  * This file is part of FFmpeg.
3  *
4  * FFmpeg is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU Lesser General Public
6  * License as published by the Free Software Foundation; either
7  * version 2.1 of the License, or (at your option) any later version.
8  *
9  * FFmpeg is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * Lesser General Public License for more details.
13  *
14  * You should have received a copy of the GNU Lesser General Public
15  * License along with FFmpeg; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17  */
18 
19 #include "config.h"
20 
21 #if HAVE_SCHED_GETAFFINITY
22 #ifndef _GNU_SOURCE
23 # define _GNU_SOURCE
24 #endif
25 #include <sched.h>
26 #endif
27 
28 #include <stddef.h>
29 #include <stdint.h>
30 #include <stdatomic.h>
31 
32 #include "attributes.h"
33 #include "cpu.h"
34 #include "cpu_internal.h"
35 #include "opt.h"
36 #include "common.h"
37 
38 #if HAVE_GETPROCESSAFFINITYMASK || HAVE_WINRT
39 #include <windows.h>
40 #endif
41 #if HAVE_SYSCTL
42 #if HAVE_SYS_PARAM_H
43 #include <sys/param.h>
44 #endif
45 #include <sys/types.h>
46 #include <sys/sysctl.h>
47 #endif
48 #if HAVE_UNISTD_H
49 #include <unistd.h>
50 #endif
51 
52 static atomic_int cpu_flags = ATOMIC_VAR_INIT(-1);
53 static atomic_int cpu_count = ATOMIC_VAR_INIT(-1);
54 
55 static int get_cpu_flags(void)
56 {
57 #if ARCH_MIPS
58  return ff_get_cpu_flags_mips();
59 #elif ARCH_AARCH64
60  return ff_get_cpu_flags_aarch64();
61 #elif ARCH_ARM
62  return ff_get_cpu_flags_arm();
63 #elif ARCH_PPC
64  return ff_get_cpu_flags_ppc();
65 #elif ARCH_RISCV
66  return ff_get_cpu_flags_riscv();
67 #elif ARCH_X86
68  return ff_get_cpu_flags_x86();
69 #elif ARCH_LOONGARCH
70  return ff_get_cpu_flags_loongarch();
71 #endif
72  return 0;
73 }
74 
75 void av_force_cpu_flags(int arg){
76  if (ARCH_X86 &&
77  (arg & ( AV_CPU_FLAG_3DNOW |
78  AV_CPU_FLAG_3DNOWEXT |
79  AV_CPU_FLAG_MMXEXT |
80  AV_CPU_FLAG_SSE |
81  AV_CPU_FLAG_SSE2 |
82  AV_CPU_FLAG_SSE2SLOW |
83  AV_CPU_FLAG_SSE3 |
84  AV_CPU_FLAG_SSE3SLOW |
85  AV_CPU_FLAG_SSSE3 |
86  AV_CPU_FLAG_SSE4 |
87  AV_CPU_FLAG_SSE42 |
88  AV_CPU_FLAG_AVX |
89  AV_CPU_FLAG_AVXSLOW |
90  AV_CPU_FLAG_XOP |
91  AV_CPU_FLAG_FMA3 |
92  AV_CPU_FLAG_FMA4 |
93  AV_CPU_FLAG_AVX2 |
94  AV_CPU_FLAG_AVX512 ))
95  && !(arg & AV_CPU_FLAG_MMX)) {
96  av_log(NULL, AV_LOG_WARNING, "MMX implied by specified flags\n");
97  arg |= AV_CPU_FLAG_MMX;
98  }
99 
100  atomic_store_explicit(&cpu_flags, arg, memory_order_relaxed);
101 }
102 
103 int av_get_cpu_flags(void)
104 {
105  int flags = atomic_load_explicit(&cpu_flags, memory_order_relaxed);
106  if (flags == -1) {
107  flags = get_cpu_flags();
108  atomic_store_explicit(&cpu_flags, flags, memory_order_relaxed);
109  }
110  return flags;
111 }
112 
113 int av_parse_cpu_caps(unsigned *flags, const char *s)
114 {
115  static const AVOption cpuflags_opts[] = {
116  { "flags" , NULL, 0, AV_OPT_TYPE_FLAGS, { .i64 = 0 }, INT64_MIN, INT64_MAX, .unit = "flags" },
117 #if ARCH_PPC
118  { "altivec" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ALTIVEC }, .unit = "flags" },
119 #elif ARCH_X86
120  { "mmx" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMX }, .unit = "flags" },
121  { "mmx2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMX2 }, .unit = "flags" },
122  { "mmxext" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMX2 }, .unit = "flags" },
123  { "sse" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE }, .unit = "flags" },
124  { "sse2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE2 }, .unit = "flags" },
125  { "sse2slow", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE2SLOW }, .unit = "flags" },
126  { "sse3" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE3 }, .unit = "flags" },
127  { "sse3slow", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE3SLOW }, .unit = "flags" },
128  { "ssse3" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSSE3 }, .unit = "flags" },
129  { "atom" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ATOM }, .unit = "flags" },
130  { "sse4.1" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE4 }, .unit = "flags" },
131  { "sse4.2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE42 }, .unit = "flags" },
132  { "avx" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVX }, .unit = "flags" },
133  { "avxslow" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVXSLOW }, .unit = "flags" },
134  { "xop" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_XOP }, .unit = "flags" },
135  { "fma3" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_FMA3 }, .unit = "flags" },
136  { "fma4" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_FMA4 }, .unit = "flags" },
137  { "avx2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVX2 }, .unit = "flags" },
138  { "bmi1" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_BMI1 }, .unit = "flags" },
139  { "bmi2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_BMI2 }, .unit = "flags" },
140  { "3dnow" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_3DNOW }, .unit = "flags" },
141  { "3dnowext", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_3DNOWEXT }, .unit = "flags" },
142  { "cmov", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_CMOV }, .unit = "flags" },
143  { "aesni", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AESNI }, .unit = "flags" },
144  { "avx512" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVX512 }, .unit = "flags" },
145  { "avx512icl", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVX512ICL }, .unit = "flags" },
146  { "slowgather", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SLOW_GATHER }, .unit = "flags" },
147 
148 #define CPU_FLAG_P2 AV_CPU_FLAG_CMOV | AV_CPU_FLAG_MMX
149 #define CPU_FLAG_P3 CPU_FLAG_P2 | AV_CPU_FLAG_MMX2 | AV_CPU_FLAG_SSE
150 #define CPU_FLAG_P4 CPU_FLAG_P3| AV_CPU_FLAG_SSE2
151  { "pentium2", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_P2 }, .unit = "flags" },
152  { "pentium3", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_P3 }, .unit = "flags" },
153  { "pentium4", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_P4 }, .unit = "flags" },
154 
155 #define CPU_FLAG_K62 AV_CPU_FLAG_MMX | AV_CPU_FLAG_3DNOW
156 #define CPU_FLAG_ATHLON CPU_FLAG_K62 | AV_CPU_FLAG_CMOV | AV_CPU_FLAG_3DNOWEXT | AV_CPU_FLAG_MMX2
157 #define CPU_FLAG_ATHLONXP CPU_FLAG_ATHLON | AV_CPU_FLAG_SSE
158 #define CPU_FLAG_K8 CPU_FLAG_ATHLONXP | AV_CPU_FLAG_SSE2
159  { "k6", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMX }, .unit = "flags" },
160  { "k62", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_K62 }, .unit = "flags" },
161  { "athlon", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_ATHLON }, .unit = "flags" },
162  { "athlonxp", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_ATHLONXP }, .unit = "flags" },
163  { "k8", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_K8 }, .unit = "flags" },
164 #elif ARCH_ARM
165  { "armv5te", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV5TE }, .unit = "flags" },
166  { "armv6", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV6 }, .unit = "flags" },
167  { "armv6t2", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV6T2 }, .unit = "flags" },
168  { "vfp", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VFP }, .unit = "flags" },
169  { "vfp_vm", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VFP_VM }, .unit = "flags" },
170  { "vfpv3", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VFPV3 }, .unit = "flags" },
171  { "neon", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_NEON }, .unit = "flags" },
172  { "setend", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SETEND }, .unit = "flags" },
173 #elif ARCH_AARCH64
174  { "armv8", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV8 }, .unit = "flags" },
175  { "neon", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_NEON }, .unit = "flags" },
176  { "vfp", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VFP }, .unit = "flags" },
177 #elif ARCH_MIPS
178  { "mmi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMI }, .unit = "flags" },
179  { "msa", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MSA }, .unit = "flags" },
180 #elif ARCH_LOONGARCH
181  { "lsx", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LSX }, .unit = "flags" },
182  { "lasx", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LASX }, .unit = "flags" },
183 #elif ARCH_RISCV
184  { "rvi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVI }, .unit = "flags" },
185  { "rvf", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVF }, .unit = "flags" },
186  { "rvd", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVD }, .unit = "flags" },
187  { "rvv-i32", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I32 }, .unit = "flags" },
188  { "rvv-f32", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 }, .unit = "flags" },
189  { "rvv-i64", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 }, .unit = "flags" },
190  { "rvv", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 }, .unit = "flags" },
191  { "rvb-basic",NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC }, .unit = "flags" },
192 #endif
193  { NULL },
194  };
195  static const AVClass class = {
196  .class_name = "cpuflags",
197  .item_name = av_default_item_name,
198  .option = cpuflags_opts,
199  .version = LIBAVUTIL_VERSION_INT,
200  };
201  const AVClass *pclass = &class;
202 
203  return av_opt_eval_flags(&pclass, &cpuflags_opts[0], s, flags);
204 }
205 
206 int av_cpu_count(void)
207 {
208  static atomic_int printed = ATOMIC_VAR_INIT(0);
209 
210  int nb_cpus = 1;
211  int count = 0;
212 #if HAVE_WINRT
213  SYSTEM_INFO sysinfo;
214 #endif
215 #if HAVE_SCHED_GETAFFINITY && defined(CPU_COUNT)
216  cpu_set_t cpuset;
217 
218  CPU_ZERO(&cpuset);
219 
220  if (!sched_getaffinity(0, sizeof(cpuset), &cpuset))
221  nb_cpus = CPU_COUNT(&cpuset);
222 #elif HAVE_GETPROCESSAFFINITYMASK
223  DWORD_PTR proc_aff, sys_aff;
224  if (GetProcessAffinityMask(GetCurrentProcess(), &proc_aff, &sys_aff))
225  nb_cpus = av_popcount64(proc_aff);
226 #elif HAVE_SYSCTL && defined(HW_NCPUONLINE)
227  int mib[2] = { CTL_HW, HW_NCPUONLINE };
228  size_t len = sizeof(nb_cpus);
229 
230  if (sysctl(mib, 2, &nb_cpus, &len, NULL, 0) == -1)
231  nb_cpus = 0;
232 #elif HAVE_SYSCTL && defined(HW_NCPU)
233  int mib[2] = { CTL_HW, HW_NCPU };
234  size_t len = sizeof(nb_cpus);
235 
236  if (sysctl(mib, 2, &nb_cpus, &len, NULL, 0) == -1)
237  nb_cpus = 0;
238 #elif HAVE_SYSCONF && defined(_SC_NPROC_ONLN)
239  nb_cpus = sysconf(_SC_NPROC_ONLN);
240 #elif HAVE_SYSCONF && defined(_SC_NPROCESSORS_ONLN)
241  nb_cpus = sysconf(_SC_NPROCESSORS_ONLN);
242 #elif HAVE_WINRT
243  GetNativeSystemInfo(&sysinfo);
244  nb_cpus = sysinfo.dwNumberOfProcessors;
245 #endif
246 
247  if (!atomic_exchange_explicit(&printed, 1, memory_order_relaxed))
248  av_log(NULL, AV_LOG_DEBUG, "detected %d logical cores\n", nb_cpus);
249 
250  count = atomic_load_explicit(&cpu_count, memory_order_relaxed);
251 
252  if (count > 0) {
253  nb_cpus = count;
254  av_log(NULL, AV_LOG_DEBUG, "overriding to %d logical cores\n", nb_cpus);
255  }
256 
257  return nb_cpus;
258 }
259 
260 void av_cpu_force_count(int count)
261 {
262  atomic_store_explicit(&cpu_count, count, memory_order_relaxed);
263 }
264 
265 size_t av_cpu_max_align(void)
266 {
267 #if ARCH_MIPS
268  return ff_get_cpu_max_align_mips();
269 #elif ARCH_AARCH64
270  return ff_get_cpu_max_align_aarch64();
271 #elif ARCH_ARM
272  return ff_get_cpu_max_align_arm();
273 #elif ARCH_PPC
274  return ff_get_cpu_max_align_ppc();
275 #elif ARCH_X86
276  return ff_get_cpu_max_align_x86();
277 #elif ARCH_LOONGARCH
278  return ff_get_cpu_max_align_loongarch();
279 #endif
280 
281  return 8;
282 }
AV_CPU_FLAG_VFP
#define AV_CPU_FLAG_VFP
Definition: cpu.h:67
av_force_cpu_flags
void av_force_cpu_flags(int arg)
Disables cpu detection and forces the specified flags.
Definition: cpu.c:75
AV_LOG_WARNING
#define AV_LOG_WARNING
Something somehow does not look correct.
Definition: log.h:186
AV_CPU_FLAG_SSE3
#define AV_CPU_FLAG_SSE3
Prescott SSE3 functions.
Definition: cpu.h:38
opt.h
cpu_count
static atomic_int cpu_count
Definition: cpu.c:53
AV_CPU_FLAG_RVB_BASIC
#define AV_CPU_FLAG_RVB_BASIC
Basic bit-manipulations.
Definition: cpu.h:89
av_cpu_force_count
void av_cpu_force_count(int count)
Overrides cpu count detection and forces the specified count.
Definition: cpu.c:260
AV_CPU_FLAG_LSX
#define AV_CPU_FLAG_LSX
Definition: cpu.h:78
av_popcount64
#define av_popcount64
Definition: common.h:152
AV_CPU_FLAG_SSE3SLOW
#define AV_CPU_FLAG_SSE3SLOW
SSE3 supported, but usually not faster.
Definition: cpu.h:39
ff_get_cpu_flags_arm
int ff_get_cpu_flags_arm(void)
Definition: cpu.c:167
AV_CPU_FLAG_3DNOW
#define AV_CPU_FLAG_3DNOW
AMD 3DNOW.
Definition: cpu.h:32
ff_get_cpu_max_align_loongarch
size_t ff_get_cpu_max_align_loongarch(void)
Definition: cpu.c:59
AV_CPU_FLAG_RVF
#define AV_CPU_FLAG_RVF
F (single precision FP)
Definition: cpu.h:83
AVOption
AVOption.
Definition: opt.h:251
ATOMIC_VAR_INIT
#define ATOMIC_VAR_INIT(value)
Definition: stdatomic.h:31
atomic_int
intptr_t atomic_int
Definition: stdatomic.h:55
ff_get_cpu_flags_loongarch
int ff_get_cpu_flags_loongarch(void)
Definition: cpu.c:49
av_get_cpu_flags
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
Definition: cpu.c:103
AV_CPU_FLAG_BMI1
#define AV_CPU_FLAG_BMI1
Bit Manipulation Instruction Set 1.
Definition: cpu.h:54
cpu_flags
static atomic_int cpu_flags
Definition: cpu.c:52
AV_CPU_FLAG_RVV_F64
#define AV_CPU_FLAG_RVV_F64
Vectors of double's.
Definition: cpu.h:88
AV_CPU_FLAG_SSSE3
#define AV_CPU_FLAG_SSSE3
Conroe SSSE3 functions.
Definition: cpu.h:41
AV_CPU_FLAG_XOP
#define AV_CPU_FLAG_XOP
Bulldozer XOP functions.
Definition: cpu.h:49
av_parse_cpu_caps
int av_parse_cpu_caps(unsigned *flags, const char *s)
Parse CPU caps from a string and update the given AV_CPU_* flags based on that.
Definition: cpu.c:113
AV_CPU_FLAG_3DNOWEXT
#define AV_CPU_FLAG_3DNOWEXT
AMD 3DNowExt.
Definition: cpu.h:37
AV_CPU_FLAG_RVV_F32
#define AV_CPU_FLAG_RVV_F32
Vectors of float's *‍/.
Definition: cpu.h:86
AV_CPU_FLAG_SLOW_GATHER
#define AV_CPU_FLAG_SLOW_GATHER
CPU has slow gathers.
Definition: cpu.h:58
AV_CPU_FLAG_AVX512
#define AV_CPU_FLAG_AVX512
AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used.
Definition: cpu.h:56
ff_get_cpu_max_align_x86
size_t ff_get_cpu_max_align_x86(void)
Definition: cpu.c:257
cpu_internal.h
s
#define s(width, name)
Definition: cbs_vp9.c:256
AV_CPU_FLAG_ARMV6
#define AV_CPU_FLAG_ARMV6
Definition: cpu.h:65
AV_LOG_DEBUG
#define AV_LOG_DEBUG
Stuff which is only useful for libav* developers.
Definition: log.h:201
ff_get_cpu_max_align_mips
size_t ff_get_cpu_max_align_mips(void)
Definition: cpu.c:119
ff_get_cpu_max_align_aarch64
size_t ff_get_cpu_max_align_aarch64(void)
Definition: cpu.c:30
AV_CPU_FLAG_SSE4
#define AV_CPU_FLAG_SSE4
Penryn SSE4.1 functions.
Definition: cpu.h:44
arg
const char * arg
Definition: jacosubdec.c:67
AV_CPU_FLAG_RVD
#define AV_CPU_FLAG_RVD
D (double precision FP)
Definition: cpu.h:84
LIBAVUTIL_VERSION_INT
#define LIBAVUTIL_VERSION_INT
Definition: version.h:85
AVClass
Describe the class of an AVClass context structure.
Definition: log.h:66
NULL
#define NULL
Definition: coverity.c:32
AV_CPU_FLAG_LASX
#define AV_CPU_FLAG_LASX
Definition: cpu.h:79
AV_CPU_FLAG_AVX512ICL
#define AV_CPU_FLAG_AVX512ICL
F/CD/BW/DQ/VL/VNNI/IFMA/VBMI/VBMI2/VPOPCNTDQ/BITALG/GFNI/VAES/VPCLMULQDQ.
Definition: cpu.h:57
av_default_item_name
const char * av_default_item_name(void *ptr)
Return the context name.
Definition: log.c:237
AV_CPU_FLAG_MSA
#define AV_CPU_FLAG_MSA
Definition: cpu.h:75
av_cpu_max_align
size_t av_cpu_max_align(void)
Get the maximum data alignment that may be required by FFmpeg.
Definition: cpu.c:265
ff_get_cpu_flags_aarch64
int ff_get_cpu_flags_aarch64(void)
Definition: cpu.c:23
AV_CPU_FLAG_CMOV
#define AV_CPU_FLAG_CMOV
supports cmov instruction
Definition: cpu.h:51
AV_CPU_FLAG_ALTIVEC
#define AV_CPU_FLAG_ALTIVEC
standard
Definition: cpu.h:60
atomic_load_explicit
#define atomic_load_explicit(object, order)
Definition: stdatomic.h:96
av_cpu_count
int av_cpu_count(void)
Definition: cpu.c:206
AV_CPU_FLAG_SSE2
#define AV_CPU_FLAG_SSE2
PIV SSE2 functions.
Definition: cpu.h:34
AV_CPU_FLAG_SETEND
#define AV_CPU_FLAG_SETEND
Definition: cpu.h:72
AV_CPU_FLAG_AVXSLOW
#define AV_CPU_FLAG_AVXSLOW
AVX supported, but slow when using YMM registers (e.g. Bulldozer)
Definition: cpu.h:48
AV_CPU_FLAG_AVX
#define AV_CPU_FLAG_AVX
AVX functions: requires OS support even if YMM registers aren't used.
Definition: cpu.h:47
AV_CPU_FLAG_FMA4
#define AV_CPU_FLAG_FMA4
Bulldozer FMA4 functions.
Definition: cpu.h:50
cpu.h
AV_CPU_FLAG_AVX2
#define AV_CPU_FLAG_AVX2
AVX2 functions: requires OS support even if YMM registers aren't used.
Definition: cpu.h:52
AV_CPU_FLAG_SSE2SLOW
#define AV_CPU_FLAG_SSE2SLOW
SSE2 supported, but usually not faster.
Definition: cpu.h:35
AV_CPU_FLAG_NEON
#define AV_CPU_FLAG_NEON
Definition: cpu.h:69
AV_CPU_FLAG_FMA3
#define AV_CPU_FLAG_FMA3
Haswell FMA3 functions.
Definition: cpu.h:53
attributes.h
AV_CPU_FLAG_MMX2
#define AV_CPU_FLAG_MMX2
SSE integer functions or AMD MMX ext.
Definition: cpu.h:31
ff_get_cpu_flags_ppc
int ff_get_cpu_flags_ppc(void)
This function MAY rely on signal() or fork() in order to make sure AltiVec is present.
Definition: cpu.c:48
AV_CPU_FLAG_SSE42
#define AV_CPU_FLAG_SSE42
Nehalem SSE4.2 functions.
Definition: cpu.h:45
common.h
AV_CPU_FLAG_RVV_I32
#define AV_CPU_FLAG_RVV_I32
Vectors of 8/16/32-bit int's *‍/.
Definition: cpu.h:85
atomic_store_explicit
#define atomic_store_explicit(object, desired, order)
Definition: stdatomic.h:90
AV_CPU_FLAG_ARMV8
#define AV_CPU_FLAG_ARMV8
Definition: cpu.h:70
len
int len
Definition: vorbis_enc_data.h:426
ff_get_cpu_flags_x86
int ff_get_cpu_flags_x86(void)
Definition: cpu.c:90
get_cpu_flags
static int get_cpu_flags(void)
Definition: cpu.c:55
AV_CPU_FLAG_ATOM
#define AV_CPU_FLAG_ATOM
Atom processor, some SSSE3 instructions are slower.
Definition: cpu.h:43
av_opt_eval_flags
int av_opt_eval_flags(void *obj, const AVOption *o, const char *val, int *flags_out)
AVClass::class_name
const char * class_name
The name of the class; usually it is the same name as the context structure type to which the AVClass...
Definition: log.h:71
AV_CPU_FLAG_VFPV3
#define AV_CPU_FLAG_VFPV3
Definition: cpu.h:68
ff_get_cpu_max_align_arm
size_t ff_get_cpu_max_align_arm(void)
Definition: cpu.c:180
AV_CPU_FLAG_ARMV5TE
#define AV_CPU_FLAG_ARMV5TE
Definition: cpu.h:64
AV_CPU_FLAG_MMX
#define AV_CPU_FLAG_MMX
standard MMX
Definition: cpu.h:29
AV_CPU_FLAG_RVI
#define AV_CPU_FLAG_RVI
I (full GPR bank)
Definition: cpu.h:82
AV_CPU_FLAG_AESNI
#define AV_CPU_FLAG_AESNI
Advanced Encryption Standard functions.
Definition: cpu.h:46
atomic_exchange_explicit
#define atomic_exchange_explicit(object, desired, order)
Definition: stdatomic.h:106
AV_CPU_FLAG_SSE
#define AV_CPU_FLAG_SSE
SSE functions.
Definition: cpu.h:33
ff_get_cpu_flags_mips
int ff_get_cpu_flags_mips(void)
Definition: cpu.c:106
AV_CPU_FLAG_MMXEXT
#define AV_CPU_FLAG_MMXEXT
SSE integer functions or AMD MMX ext.
Definition: cpu.h:30
ff_get_cpu_max_align_ppc
size_t ff_get_cpu_max_align_ppc(void)
Definition: cpu.c:152
AV_CPU_FLAG_BMI2
#define AV_CPU_FLAG_BMI2
Bit Manipulation Instruction Set 2.
Definition: cpu.h:55
AV_CPU_FLAG_VFP_VM
#define AV_CPU_FLAG_VFP_VM
VFPv2 vector mode, deprecated in ARMv7-A and unavailable in various CPUs implementations.
Definition: cpu.h:71
AV_CPU_FLAG_MMI
#define AV_CPU_FLAG_MMI
Definition: cpu.h:74
AV_OPT_TYPE_FLAGS
@ AV_OPT_TYPE_FLAGS
Definition: opt.h:224
flags
#define flags(name, subs,...)
Definition: cbs_av1.c:561
av_log
#define av_log(a,...)
Definition: tableprint_vlc.h:27
AV_CPU_FLAG_RVV_I64
#define AV_CPU_FLAG_RVV_I64
Vectors of 64-bit int's *‍/.
Definition: cpu.h:87
ff_get_cpu_flags_riscv
int ff_get_cpu_flags_riscv(void)
Definition: cpu.c:31
AV_OPT_TYPE_CONST
@ AV_OPT_TYPE_CONST
Definition: opt.h:234
AV_CPU_FLAG_ARMV6T2
#define AV_CPU_FLAG_ARMV6T2
Definition: cpu.h:66
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