30 #define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
32 #if HAVE_SYS_HWPROBE_H
33 #include <sys/hwprobe.h>
34 #elif HAVE_ASM_HWPROBE_H
35 #include <asm/hwprobe.h>
36 #include <sys/syscall.h>
39 static int __riscv_hwprobe(
struct riscv_hwprobe *pairs,
size_t pair_count,
43 return syscall(__NR_riscv_hwprobe, pairs, pair_count,
cpu_count,
cpus,
51 #if HAVE_SYS_HWPROBE_H || HAVE_ASM_HWPROBE_H
52 struct riscv_hwprobe pairs[] = {
53 { RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0 },
54 { RISCV_HWPROBE_KEY_IMA_EXT_0, 0 },
55 { RISCV_HWPROBE_KEY_CPUPERF_0, 0 },
59 if (pairs[0].
value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA)
61 if (pairs[1].
value & RISCV_HWPROBE_IMA_FD)
63 #ifdef RISCV_HWPROBE_IMA_V
64 if (pairs[1].
value & RISCV_HWPROBE_IMA_V)
68 #ifdef RISCV_HWPROBE_EXT_ZBA
69 if (pairs[1].
value & RISCV_HWPROBE_EXT_ZBA)
72 #ifdef RISCV_HWPROBE_EXT_ZBB
73 if (pairs[1].
value & RISCV_HWPROBE_EXT_ZBB)
75 #if defined (RISCV_HWPROBE_EXT_ZBA) && defined (RISCV_HWPROBE_EXT_ZBS)
76 if ((pairs[1].
value & RISCV_HWPROBE_EXT_ZBA) &&
77 (pairs[1].
value & RISCV_HWPROBE_EXT_ZBB) &&
78 (pairs[1].
value & RISCV_HWPROBE_EXT_ZBS))
82 #ifdef RISCV_HWPROBE_EXT_ZVBB
83 if (pairs[1].
value & RISCV_HWPROBE_EXT_ZVBB)
86 switch (pairs[2].
value & RISCV_HWPROBE_MISALIGNED_MASK) {
87 case RISCV_HWPROBE_MISALIGNED_FAST:
95 const unsigned long hwcap = getauxval(AT_HWCAP);
97 if (hwcap & HWCAP_RV(
'I'))
99 if (hwcap & HWCAP_RV(
'F'))
101 if (hwcap & HWCAP_RV(
'D'))
103 if (hwcap & HWCAP_RV(
'B'))
108 if (hwcap & HWCAP_RV(
'V'))
117 #if defined (__riscv_flen) && (__riscv_flen >= 32)
119 #if (__riscv_flen >= 64)
130 #if defined (__riscv_b) || \
131 (defined (__riscv_zba) && defined (__riscv_zbb) && defined (__riscv_zbs))
136 #ifdef __riscv_vector
138 #if __riscv_v_elen >= 64
141 #if __riscv_v_elen_fp >= 32
143 #if __riscv_v_elen_fp >= 64