[FFmpeg-cvslog] Merge commit '71a0472114574993df7035f4de9aa007e03817b8'

Clément Bœsch git at videolan.org
Tue Jan 24 20:22:24 EET 2017


ffmpeg | branch: master | Clément Bœsch <u at pkh.me> | Tue Jan 24 19:17:38 2017 +0100| [9f1c81e5ec90fcfa7efc088d769b9e339a252bfb] | committer: Clément Bœsch

Merge commit '71a0472114574993df7035f4de9aa007e03817b8'

* commit '71a0472114574993df7035f4de9aa007e03817b8':
  checkasm: arm: report the first clobbered register in checkasm_checked_call

Also includes 446353ea18, 59aeed93e4, and 37961044c6 to avoid breaking
too much stuff.

Merged-by: Clément Bœsch <u at pkh.me>

> http://git.videolan.org/gitweb.cgi/ffmpeg.git/?a=commit;h=9f1c81e5ec90fcfa7efc088d769b9e339a252bfb
---

 tests/checkasm/arm/checkasm.S | 75 ++++++++++++++++++++++++++++---------------
 1 file changed, 49 insertions(+), 26 deletions(-)

diff --git a/tests/checkasm/arm/checkasm.S b/tests/checkasm/arm/checkasm.S
index 62a91c1..0cbf32e 100644
--- a/tests/checkasm/arm/checkasm.S
+++ b/tests/checkasm/arm/checkasm.S
@@ -22,6 +22,12 @@
 
 #include "libavutil/arm/asm.S"
 
+/* override fpu so that NEON instructions are rejected */
+#if HAVE_VFP
+.fpu            vfp
+ELF     .eabi_attribute 10, 0           @ suppress Tag_FP_arch
+#endif
+
 const register_init, align=3
     .quad 0x21f86d66c8ca00ce
     .quad 0x75b6ba21077c48ad
@@ -33,8 +39,12 @@ const register_init, align=3
     .quad 0x249214109d5d1c88
 endconst
 
-const error_message
-    .asciz "failed to preserve register"
+const error_message_fpscr
+    .asciz "failed to preserve register FPSCR, changed bits: %x"
+error_message_gpr:
+    .asciz "failed to preserve register r%d"
+error_message_vfp:
+    .asciz "failed to preserve register d%d"
 endconst
 
 @ max number of args used by any asm function.
@@ -79,39 +89,45 @@ function checkasm_checked_call_\variant, export=1
 
     push        {r0, r1}
     movrel      r12, register_init
-    mov         r3,  #0
 .ifc \variant, vfp
-.macro check_reg_vfp, dreg, inc=8
-    ldrd        r0,  r1,  [r12], #\inc
-    vmov        r2,  lr,  \dreg
-    eor         r0,  r0,  r2
-    eor         r1,  r1,  lr
-    orr         r3,  r3,  r0
-    orr         r3,  r3,  r1
+.macro check_reg_vfp, dreg, offset
+    ldrd        r2,  r3,  [r12, #8 * (\offset)]
+    vmov        r0,  lr,  \dreg
+    eor         r2,  r2,  r0
+    eor         r3,  r3,  lr
+    orrs        r2,  r2,  r3
+    bne         4f
 .endm
 
-.irp n, 8, 9, 10, 11, 12, 13, 14
-    check_reg_vfp d\n
+.irp n, 8, 9, 10, 11, 12, 13, 14, 15
+    @ keep track of the checked double/SIMD register
+    mov         r1,  #\n
+    check_reg_vfp d\n, \n-8
 .endr
-    check_reg_vfp d15, -56
 .purgem check_reg_vfp
 
-    fmrx        r0,  FPSCR
-    ldr         r1,  [sp, #8]
-    eor         r0,  r0,  r1
+    fmrx        r1,  FPSCR
+    ldr         r3,  [sp, #8]
+    eor         r1,  r1,  r3
+    @ Ignore changes in bits 0-4 and 7
+    bic         r1,  r1,  #0x9f
     @ Ignore changes in the topmost 5 bits
-    lsl         r0,  r0,  #5
-    orr         r3,  r3,  r0
+    bics        r1,  r1,  #0xf8000000
+    bne         3f
 .endif
 
+    @ keep track of the checked GPR
+    mov         r1,  #4
 .macro check_reg reg1, reg2=
-    ldrd        r0,  r1,  [r12], #8
-    eor         r0,  r0,  \reg1
-    orrs        r3,  r3,  r0
+    ldrd        r2,  r3,  [r12], #8
+    eors        r2,  r2,  \reg1
+    bne         2f
+    add         r1,  r1,  #1
 .ifnb \reg2
-    eor         r1,  r1,  \reg2
-    orrs        r3,  r3,  r1
+    eors        r3,  r3,  \reg2
+    bne         2f
 .endif
+    add         r1,  r1,  #1
 .endm
     check_reg   r4,  r5
     check_reg   r6,  r7
@@ -124,9 +140,16 @@ function checkasm_checked_call_\variant, export=1
     check_reg   r10, r11
 .purgem check_reg
 
-    beq         0f
-
-    movrel      r0, error_message
+    b           0f
+4:
+    movrel      r0, error_message_vfp
+    b           1f
+3:
+    movrel      r0, error_message_fpscr
+    b           1f
+2:
+    movrel      r0, error_message_gpr
+1:
     blx         X(checkasm_fail_func)
 0:
     pop         {r0, r1}


======================================================================

diff --cc tests/checkasm/arm/checkasm.S
index 62a91c1,989f613..0cbf32e
--- a/tests/checkasm/arm/checkasm.S
+++ b/tests/checkasm/arm/checkasm.S
@@@ -22,6 -22,6 +22,12 @@@
  
  #include "libavutil/arm/asm.S"
  
++/* override fpu so that NEON instructions are rejected */
++#if HAVE_VFP
++.fpu            vfp
++ELF     .eabi_attribute 10, 0           @ suppress Tag_FP_arch
++#endif
++
  const register_init, align=3
      .quad 0x21f86d66c8ca00ce
      .quad 0x75b6ba21077c48ad
@@@ -33,8 -33,12 +39,12 @@@
      .quad 0x249214109d5d1c88
  endconst
  
- const error_message
-     .asciz "failed to preserve register"
+ const error_message_fpscr
 -    .asciz "failed to preserve register FPSCR"
 -const error_message_gpr
++    .asciz "failed to preserve register FPSCR, changed bits: %x"
++error_message_gpr:
+     .asciz "failed to preserve register r%d"
 -const error_message_vfp
++error_message_vfp:
+     .asciz "failed to preserve register d%d"
  endconst
  
  @ max number of args used by any asm function.
@@@ -79,39 -83,42 +89,45 @@@ function checkasm_checked_call_\variant
  
      push        {r0, r1}
      movrel      r12, register_init
-     mov         r3,  #0
  .ifc \variant, vfp
- .macro check_reg_vfp, dreg, inc=8
-     ldrd        r0,  r1,  [r12], #\inc
-     vmov        r2,  lr,  \dreg
-     eor         r0,  r0,  r2
-     eor         r1,  r1,  lr
-     orr         r3,  r3,  r0
-     orr         r3,  r3,  r1
+ .macro check_reg_vfp, dreg, offset
 -    vldr        d0,  [r12, #8 * (\offset)]
 -    veor        d0,  d0,  \dreg
 -    vmov        r2,  r3,  d0
++    ldrd        r2,  r3,  [r12, #8 * (\offset)]
++    vmov        r0,  lr,  \dreg
++    eor         r2,  r2,  r0
++    eor         r3,  r3,  lr
+     orrs        r2,  r2,  r3
+     bne         4f
  .endm
  
- .irp n, 8, 9, 10, 11, 12, 13, 14
-     check_reg_vfp d\n
+ .irp n, 8, 9, 10, 11, 12, 13, 14, 15
+     @ keep track of the checked double/SIMD register
+     mov         r1,  #\n
+     check_reg_vfp d\n, \n-8
  .endr
-     check_reg_vfp d15, -56
  .purgem check_reg_vfp
  
--    fmrx        r0,  FPSCR
-     ldr         r1,  [sp, #8]
-     eor         r0,  r0,  r1
++    fmrx        r1,  FPSCR
+     ldr         r3,  [sp, #8]
 -    eor         r0,  r0,  r3
++    eor         r1,  r1,  r3
++    @ Ignore changes in bits 0-4 and 7
++    bic         r1,  r1,  #0x9f
      @ Ignore changes in the topmost 5 bits
-     lsl         r0,  r0,  #5
-     orr         r3,  r3,  r0
 -    lsls        r0,  r0,  #5
++    bics        r1,  r1,  #0xf8000000
+     bne         3f
  .endif
  
+     @ keep track of the checked GPR
+     mov         r1,  #4
  .macro check_reg reg1, reg2=
-     ldrd        r0,  r1,  [r12], #8
-     eor         r0,  r0,  \reg1
-     orrs        r3,  r3,  r0
+     ldrd        r2,  r3,  [r12], #8
+     eors        r2,  r2,  \reg1
+     bne         2f
+     add         r1,  r1,  #1
  .ifnb \reg2
-     eor         r1,  r1,  \reg2
-     orrs        r3,  r3,  r1
+     eors        r3,  r3,  \reg2
+     bne         2f
  .endif
+     add         r1,  r1,  #1
  .endm
      check_reg   r4,  r5
      check_reg   r6,  r7



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