[FFmpeg-devel] [PATCHv2 0/10] RISC-V V floating point DSP

[Rémi Denis-Courmont]

Le sunnuntaina 4. syyskuuta 2022, 20.48.26 EEST Lynne a écrit :
> > The pointer arithmetic could be slightly optimised with SH2ADD and
> > SH3ADD instructions from the Zvba extension. This would require more
> > conditional code, or requiring support for Zvba for probably neglible
> > performance gains though.
> 
> Did you test on real hardware or a VM?

I don't think we will see real and conforming RV64GV hardware this year, 
unless you count FPGAs. I hope we can get affordable stuff in 2023H1.

This is running on simulator. But since the code is already (AFAICT) using the 
largest possible grouping, there won't be that much room for further 
optimisations, other maybe than to add prefetching hints. In that sense, RVV 
is really nice in how it makes unrolling almost unnecessary/effortless.

The code is also already laid out to leverage multiple issue if available. 
RISC-V does not have post-index addressing modes, so the interleaving a fair 
amount of pointer arithmetic is unavoidable.

> If the former, what does checkasm --bench report?

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