[FFmpeg-devel] [PATCH 1/3] lavu: detect RISC-V F extension (i.e. float)

[Lynne]

Sep 14, 2022, 19:50 by remi at remlab.net:

> From: Rémi Denis-Courmont <remi at remlab.net>
>
> This introduces compile-tim and run-time CPU detection on RISC-V. In
> practice, I doubt that FFmpeg will ever see a RISC-V CPU without the F
> extension, and if it does, it probably won't have run-time detection.
> So the flag is essentially always set.
>
> But as things stand, checkasm wants it that way, and we are nowhere
> near running short on CPU flag bits on that platform.
> ---
>  libavutil/cpu.c           |  4 ++++
>  libavutil/cpu.h           |  3 +++
>  libavutil/cpu_internal.h  |  1 +
>  libavutil/riscv/Makefile  |  1 +
>  libavutil/riscv/cpu.c     | 44 +++++++++++++++++++++++++++++++++++++++
>  tests/checkasm/checkasm.c |  2 ++
>  6 files changed, 55 insertions(+)
>  create mode 100644 libavutil/riscv/Makefile
>  create mode 100644 libavutil/riscv/cpu.c
>
> diff --git a/libavutil/cpu.c b/libavutil/cpu.c
> index 0035e927a5..6e9b8c5f58 100644
> --- a/libavutil/cpu.c
> +++ b/libavutil/cpu.c
> @@ -62,6 +62,8 @@ static int get_cpu_flags(void)
>  return ff_get_cpu_flags_arm();
>  #elif ARCH_PPC
>  return ff_get_cpu_flags_ppc();
> +#elif ARCH_RISCV
> +    return ff_get_cpu_flags_riscv();
>  #elif ARCH_X86
>  return ff_get_cpu_flags_x86();
>  #elif ARCH_LOONGARCH
> @@ -178,6 +180,8 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
>  #elif ARCH_LOONGARCH
>  { "lsx",      NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LSX      },    .unit = "flags" },
>  { "lasx",     NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LASX     },    .unit = "flags" },
> +#elif ARCH_RISCV
> +        { "float",    NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_F        },    .unit = "flags" },
>  #endif
>  { NULL },
>  };
> diff --git a/libavutil/cpu.h b/libavutil/cpu.h
> index 9711e574c5..71ae70bcbd 100644
> --- a/libavutil/cpu.h
> +++ b/libavutil/cpu.h
> @@ -78,6 +78,9 @@
>  #define AV_CPU_FLAG_LSX          (1 << 0)
>  #define AV_CPU_FLAG_LASX         (1 << 1)
>  
> +// RISC-V Vector extension
> +#define AV_CPU_FLAG_F            (1 << 0)
>

Can you prefix that with RV (FLAG_RVF) like the function?